ersa error resilient system architecture Bend Texas

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ersa error resilient system architecture Bend, Texas

Full-text · Conference Paper · Jan 2016 Santanu SarmaTiago MückMajid Shoushtari+1 more author ...Nikil DuttRead full-textTECS2014-a138-sabry"However, our proposal can be surpassed by SW mitigation techniques, that utilize either backward or forward The first integrated circuit (IC) was built a decade later, with the first microprocessor designed in the early 1970s. In contrast to task mapping where the network topology is predefined, fault-tolerance in the communication network design involves the reliability evaluation of the network topology. First, we present SmartBalance, a cross-layer sensing-driven Linux load balancer for energy efficient task execution on hetergoenous MPSOCs.

Generated Sat, 15 Oct 2016 06:49:54 GMT by s_wx1131 (squid/3.5.20) ERROR The requested URL could not be retrieved The following error was encountered while trying to retrieve the URL: Connection Showcasing the latest advances in very-large-scale integrated (VLSI) circuits, VLSI: Circuits for Emerging Applications provides a balanced view of industrial and academic developments beyond silicon and complementary metal–oxide–semiconductor (CMOS) technology. Error injection experiments on a multi-core ERSA hardware prototype demonstrate that, even at very high error rates of 20,000 errors/second/core or 2x10-4 error/cycle/core (with errors injected in architecturally-visible registers), ERSA maintains Error injection experiments on a multi-core ERSA hardware prototype demonstrate that, even at very high error rates of 20,000 errors/second/core or 2x10-4 error/cycle/core (with errors injected in architecturally-visible registers), ERSA maintains

Moreover, we demonstrate the effectiveness of ERSA in tolerating high rates of static memory errors that are characteristic of emerging challenges such as Vccmin problems and erratic bit errors. Here are the instructions how to enable JavaScript in your web browser. Institutional Sign In By Topic Aerospace Bioengineering Communication, Networking & Broadcasting Components, Circuits, Devices & Systems Computing & Processing Engineered Materials, Dielectrics & Plasmas Engineering Profession Fields, Waves & Electromagnetics General Therefore, to gain better energy efficiency, these knobs can be dynamically adjusted during an application's execution, based on the quality of generated results. "[Show abstract] [Hide abstract] ABSTRACT: We introduce the

Your cache administrator is webmaster. Subscribe Enter Search Term First Name / Given Name Family Name / Last Name / Surname Publication Title Volume Issue Start Page Search Basic Search Author Search Publication Search Advanced Search The system returned: (22) Invalid argument The remote host or network may be down. Please try the request again.

We propose a heuristic based on divide-and-conquer approach and validate the quality of the results with an exhaustive search for small graphs. Syst.20161 ExcerptInput responsiveness: using canary inputs to dynamically steer approximationMichael Laurenzano, Parker Hill, Mehrzad Samadi, Scott A. Although carefully collected, accuracy cannot be guaranteed. In this paper, we apply the idea of k-node fault tolerant graph to address the challenge of reliable network design.

What people are saying-Write a reviewWe haven't found any reviews in the usual places.Other editions - View allVLSI: Circuits for Emerging ApplicationsTomasz WojcickiLimited preview - 2014About the author(2014)Tomasz Wojcicki is currently Generated Sat, 15 Oct 2016 06:49:53 GMT by s_wx1131 (squid/3.5.20) ERROR The requested URL could not be retrieved The following error was encountered while trying to retrieve the URL: Connection For full functionality of ResearchGate it is necessary to enable JavaScript. Did you know your Organization can subscribe to the ACM Digital Library?

While task mapping techniques have been heavily investigated in the past decade [8], design of reliable network topologies according to the application-level task pattern receives relatively less focus. "[Show abstract] [Hide The effectiveness of proposed methodology is demonstrated with real multiprocessor computational task using a commercial system-level design environment. They help us live longer and more comfortably, and do more, faster. rgreq-52b91cf656158f94ac17b78b7f07eab6 false Homeaboutaffiliatesresearcheventscareersconnectvisitors About The Forum Benefits Visiting Scholars Openness in Research Provision Policies Affecting Industrial Affiliates Program Memberships How to Join The Forum Forum Staff Forum Leadership Newsletter (PDF) Wiki

Get Help About IEEE Xplore Feedback Technical Support Resources and Help Terms of Use What Can I Access? While resilience of RMS applications to errors in low-order bits of data is well-known, execution of such applications on error-prone hardware significantly degrades output quality (due to high-order bit errors and These techniques are effective when the target system can tolerate erroneous operation [Leem et al. 2010], and when best-effort (not guaranteed) error correction is satisfactory. " Full-text · Dataset · Oct We present Error Resilient System Architecture (ERSA), a robust system architecture which targets emerging killer applications such as recognition, mining, and synthesis (RMS) with inherent error resilience, and ensures high degrees

Using the concept of configurable reliability, ERSA platforms may also be adapted for general-purpose applications that are less resilient to errors (but at higher costs).Extracted Key PhrasesError ToleranceMemory ErrorWireless CommunicationArchitecture LevelGeneralpurpose Please try the request again. His current research interests include reliable computer architecture and computing models for robust systems. Copyright © 2016 ACM, Inc.

Use of this web site signifies your agreement to the terms and conditions. Traditional redundancy techniques are expensive for designing energy-efficient systems that are resilient to high error rates. Cookies help us deliver our services. The ACM Guide to Computing Literature All Tags Export Formats Save to Binder Skip to MainContent IEEE Xplore Digital Library IEEE-SA IEEE Spectrum More Sites cartProfile.cartItemQty Create Account

on CAD of Integrated Circuits and…2010View PDFCiteSaveAbstractThere is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. We present two sample use cases that exemplify the cross-layer virtual/physical sensing and actuation approach. Embedded Comput. He previously worked at the Institute of Electron Technology, Warsaw, Poland, and at MOSAID Technologies, Inc., Ottawa, Ontario, Canada (now Conversant Intellectual Property Management).

ERSA achieves high error resilience to high-order bit errors and control errors (in addition to low-order bit errors) using a judicious combination of 3 key ideas: (1) asymmetric reliability in many-core US & Canada: +1 800 678 4333 Worldwide: +1 732 981 0060 Contact & Support About IEEE Xplore Contact Us Help Terms of Use Nondiscrimination Policy Sitemap Privacy & Opting Out Jacobson Nokia Research Center, Palo Alto, CA Subhasish Mitra Stanford University, Stanford, CA 2010 Article Bibliometrics ·Downloads (6 Weeks): 1 ·Downloads (12 Months): 20 ·Downloads (cumulative): 161 ·Citation Count: 58 All this is possible because of the relentless search for new materials, circuit designs, and ideas happening on a daily basis at industrial and academic institutions around the globe.

By using our services, you agree to our use of cookies.Learn moreGot itMy AccountSearchMapsYouTubePlayNewsGmailDriveCalendarGoogle+TranslatePhotosMoreShoppingWalletFinanceDocsBooksBloggerContactsHangoutsEven more from GoogleSign inHidden - Recently the world celebrated the 60th anniversary of the invention of We present Error Resilient System Architecture (ERSA), a low-cost robust system architecture for emerging killer probabilistic applications such as Recognition, Mining and Synthesis (RMS) applications.