gain error correction technique for pipelined analog-to-digital converters Twin Mountain New Hampshire

Address 260 Cottage St Ste B, Littleton, NH 03561
Phone (603) 444-3388
Website Link http://profiletechnologies.com
Hours

gain error correction technique for pipelined analog-to-digital converters Twin Mountain, New Hampshire

The data latency of pipelined ADCs is of little concern in most applications. Unabled to verify parameters Could not contact recaptcha for validation I am not a robot * 291935814 Electronics Letters — Recommend this title to your library Thank youYour recommendation has been Figure 3. The CMOS MAX1425 (10-bit, 20Msps) and the MAX1426 (10-bit, 10Msps) family uses the popular 1.5-bit-per-stage architecture; each stage resolves one bit with 0.5-bit overlap.

IEEE J. The system returned: (22) Invalid argument The remote host or network may be down. Galton 1 View affiliations Affiliations: 1: Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, USA Source: Volume 36, Issue 7, 30 March 2000, p. 617 – Note when a stage finishes processing a sample, determining the bits, and passing the residue to the next stage, it can then start processing the next sample received from the sample-and-hold

P., & Franca, J. T., Stamatopoulos, N., Karadamoglou, K., & Paschalidis, V. (2005). 10-Bit, low power, successive approximation, digitally auto-zeroed CMOS ADC core for the NASA TRIO smart sensor system on a Chip. In a pipeline, however, to a first order the complexity only increases linearly, not exponentially, with the resolution. This pipelining action is the reason for the high throughput.

A 200 MHz 4.8 mW 3 V fully differential CMOS sample-and-hold circuit with low hold pedestal. C., & Chris, T. (1997). Generated Mon, 17 Oct 2016 03:09:29 GMT by s_ac15 (squid/3.5.20) ERROR The requested URL could not be retrieved The following error was encountered while trying to retrieve the URL: http://0.0.0.10/ Connection Generated Mon, 17 Oct 2016 03:09:29 GMT by s_ac15 (squid/3.5.20)

At sampling rates obtainable by both pipeline and flash converters, a pipelined device usually has much lower power consumption than a flash. In general, for about 12 bits of accuracy or higher, some form of capacitor/resistor trimming or digital calibration is required, especially for the first two stages. Register now for a free account in order to: Sign in to various IEEE sites with a single account Manage your membership Get member discounts Personalize your experience Manage your profile Subscribe Enter Search Term First Name / Given Name Family Name / Last Name / Surname Publication Title Volume Issue Start Page Search Basic Search Author Search Publication Search Advanced Search

Learn more about IET membership Recommend to library You must fill out fields marked with: * Librarian details Name:* Email:* Your details Name:* Email:* Department:* Why are you recommending this title? C., & Krummenacher, F. (1984). X. (2008). Once the third MDAC is calibrated, it can be used to calibrate the second MDAC in a similar fashion.

In these methods, few unit capacitors of main S/H-capacitor are separated for correction. The content on this webpage is protected by copyright laws of the United States and of foreign countries. A pipelined 5-Msample/s 9-bit analog-to-digital converter. A 1.5-bit flash ADC (two comparators) compares the analog input to the comparator thresholds, which are -0.25V and +0.25V in this example.

These three methods are specifically proposed for switched- capacitor (SC) S/H circuits. VIN Transfer Characteristic(See Figure 4) Digital Output (-1 , 0, or +1) Decimal Place Value VRESIDUE (VIN for the Next Stage) 1 0.6 Region 3 +1 64 2 × 0.6 - Random errors effects in matched MOS capacitors and current sources. Matching properties of MOS transistors.

Your cache administrator is webmaster. A. The implication is that none of the flash ADCs in Figure 1 has to be as accurate as the entire ADC. C. (1997).

This process is called "1-bit overlap" between adjacent stages. C. The extra one to three bits are required by the digital calibration to quantize the error terms to greater accuracy than the ADC itself; the extra bits are also discarded to Create email alert Get permissions Export citations BibTEX Endnote Plain text RefWorks Key NNew content Free content Open access content Subscribed content Trial content

As a result, a pipelined ADC cannot match the speed of a well-designed flash ADC. Likewise, once the second and third MDAC are calibrated, they are used to calibrate the first MDAC. J., & Welbers, A. In the example in Figure 1, this latency is about three cycles (see Figure 2).

Sigma-delta converters trade speed for resolution. A 1-bit ADC would have two regions (1/High or 0/Low) and a 2-bit ADC would have four regions (00, 01, 10, and 11) on the transfer characteristics. A 220-M sample/s CMOS sample-and-hold circuit using double-sampling. Institutional Sign In By Topic Aerospace Bioengineering Communication, Networking & Broadcasting Components, Circuits, Devices & Systems Computing & Processing Engineered Materials, Dielectrics & Plasmas Engineering Profession Fields, Waves & Electromagnetics General

contact us. © 2015 Maxim Integrated | Contact Us | Careers | Legal | Privacy | Cookie Policy | Site Map | Follow Us: © 2015 Maxim Integrated | Contact Us Lewis , P.R. Part of Springer Nature. Versus the Sigma-Delta Converter Traditionally, oversampling/sigma-delta-type converters commonly used in digital audio have a limited bandwidth of about 22kHz.

J. Analog Integr Circ Sig Process (2011) 68: 357. Therefore, a digital output of 77 will correspond to 77/127 = 0.606V, which is a good approximation of the sampled analog input applied to the pipelined ADC. Try again.

A sigma-delta converter needs no special trimming/calibration, even for 16 to 18 bits of resolution. Pipelined ADC Architecture Figure 1 shows a block diagram of a 12-bit pipelined ADC. doi:10.1007/s10470-011-9626-5 179 Views AbstractThis paper describes a simple offset error (OEC) and two gain error (GEC) correction methods for an analog–digital converter (ADC), which use a dedicated sample-and-hold (S/H) circuit. The 1.5-bit indicates that there are three regions on the VRESIDUE vs.

The backend digital filters take care of that task. As the number of bits increases (for example, 12 bits or higher) with digital error correction, however, each stage would need to incorporate a 6- to 7-bit flash ADC. Electronic Letters, 35(3), 188–189.CrossRefGoogle Scholar12.Shi, X., Matsumoto, H., & Murao, K. (2000) Gain- and offset-compensated non-inversting sc circuits. They also require no steep rolling-off anti-alias filter at the analog inputs, because the sampling rate is much higher than the effective bandwidth.

Download Download, PDF Format(70kB) © Oct 02, 2001, Maxim Integrated Products, Inc. The digital decimation filter is also nontrivial to design, and consumes a lot of silicon area. US & Canada: +1 800 678 4333 Worldwide: +1 732 981 0060 Contact & Support About IEEE Xplore Contact Us Help Terms of Use Nondiscrimination Policy Sitemap Privacy & Opting Out The second GEC method uses charge sharing method between capacitors.KeywordsAnalog-to-digital-conversionDigital-to- analog-conversionOffset-errorGain-errorFactory calibrationTestingSample-and-holdReferences1.Shyu, J.-B., Temes, G.

Digital Calibration The MAX1200 (16-bit, 1Msps), MAX1201 (14-bit 2Msps), and MAX1205 (14-bit, 1Msps) family¹ of ADCs employs digital calibration to ensure excellent accuracy and dynamic performance.