fingerprinting bounding soft-error detection latency and bandwidth Mcmillan Michigan

Address 131 River St, Manistique, MI 49854
Phone (906) 341-2928
Website Link

fingerprinting bounding soft-error detection latency and bandwidth Mcmillan, Michigan

The increasing scaling technology and subsequent supply voltage reductions, together with temperature fluctuations, augment the susceptibility of architectures to errors.With the development of CMPs, the interest for using parallel applications has The system returned: (22) Invalid argument The remote host or network may be down. Sánchez D, Aragón JL, García JM (2008) Evaluating dynamic core coupling in a scalable tiled-cmp architecture. LaFrieda C, Ipek E, Martinez JF, Manohar R (2007) Utilizing dynamically coupled cores to form a resilient chip multiprocessor.

In: Proc of the 7th int workshop on duplicating, deconstructing, and debunking (WDDD’08). In: The 2nd workshop on system effects of logic soft errors Google Scholar28. The system returned: (22) Invalid argument The remote host or network may be down. In: Proc of the 29th annual int’ symp on computer architecture (ISCA’02), Anchorage, Alaska Google Scholar20.

Bartlett J, Gray J, Horst B (1987) Fault tolerance in tandem computer systems. The processors in a dual modular redundant pair periodically exchange and compare fingerprints to corroborate each other's correctness. In: Proc of the 30th annual int’ symp on computer architecture (ISCA’03), San Diego, California Google Scholar7. In conjunction with ISCA’08, Beijing, China Google Scholar26.

SIGN IN SIGN UP Fingerprinting: bounding soft-error detection latency and bandwidth Full Text: PDF Get this Article Authors: Jared C. Wenisch TF, Ailamaki A, Falsafi B, Moshovos A (2007) Mechanisms for store-wait-free multiprocessors, pp 266–277 34. In: Proc of the int’ symp on microarchitecture (MICRO’02), Istanbul, Turkey. In Euro-Par, the ?eld of parallel computing is divided into the four broad categories of t- ory, high performance, cluster and grid, and distributed and mobile computing.

International VS, Weaver DL, Germond T (1992) The sparc architecture manual. Nowatzyk Carnegie Mellon University, Pittsburgh, PA 2004 Article Bibliometrics ·Downloads (6 Weeks): 6 ·Downloads (12 Months): 50 ·Downloads (cumulative): 1,195 ·Citation Count: 32 Published in: ·Proceeding ASPLOS XI Proceedings Smolens Carnegie Mellon University, Pittsburgh, PA Brian T. RMT (Redundant Multi-Threading) is a family of techniques based on SMT (Simultaneous Multi-Threading) processors in which two independent threads (master and slave), fed with the same inputs, redundantly execute the same

Euro-Par 2009 was the 15th conference in the Euro-Par series, and was - ganized by the Parallel and Distributed Systems Group of Delft University of Technology in Delft, The Netherlands. Vijaykumar T, Pomeranz I, Cheng K (2002) Transient fault recovery using simultaneous multithreading. Wang NJ, Patel SJ (2006) Restore: Symptom-based soft error detection in microprocessors. Cypress Semiconductor Corporation Copyright information© Springer Science+Business Media, LLC 2011Authors and AffiliationsDaniel Sánchez1Email authorJuan L. Aragón1José M. García11.Departamento de Ingeniería y Tecnología de ComputadoresUniversidad de MurciaMurciaSpain About this article Print ISSN 0920-8542 Online ISSN 1573-0484 Publisher Name Springer

Selse (2006) Selse ii final remarks. Electronics Design, Strategy, News (EDN) pp 69–74. Ziegler J, Lanford WA (1981) The effect of sea level cosmic rays on electronic devices. Google Scholar17.

Taylor MB, Kim J, Miller J, Wentzlaff D, Ghodrat F, Greenwald B, Hoffman H, Johnson P, Lee JW, Lee W, Ma A, Saraf A, Seneski M, Shnidman N, Strumpen V, Frank US & Canada: +1 800 678 4333 Worldwide: +1 732 981 0060 Contact & Support About IEEE Xplore Contact Us Help Terms of Use Nondiscrimination Policy Sitemap Privacy & Opting Out Morgan Kauffman, San Mateo Google Scholar19. doi:10.1145/237090.237140.

REPAS architecture only needs few extra hardware since the redundant execution is performed within 2-way SMT cores in which the majority of hardware is shared. J Supercomput (2012) 61: 997. The target audience of Euro-Par c- sists of researchers in parallel computing in academic departments, government laboratories, and industrial organizations. Mastipuram R, Wee EC (2004) Soft error’s impact on system reliability.

Li ML, Sasanka R, Adve SV, Chen KY, Debes E (2005) The alpbench benchmark suite for complex multimedia applications. Generated Fri, 14 Oct 2016 07:19:53 GMT by s_ac4 (squid/3.5.20) Please try the request again. Accessibility Homepage Navigation within EPFL sites Navigation within this site Jump to search field Jump to page content Technical contact You are Prospective students portal Bachelor, Master, PhD Exchange student Students

doi:10.1109/2.982916 15. Rotenberg E (1999) Ar-smt: A microarchitectural approach to fault tolerance in microprocessors. Mukherjee S, Kontz M, Reinhardt SK (2002) Detailed design and evaluation of redundant multithreading alternatives. IEEE MICRO 22(2):25–35 CrossRefGoogle Scholar31. Google Scholar21. Hoe Carnegie Mellon University, Pittsburgh, PA Andreas G. TABLE OF CONTENTSChapter 1: Introduction Chapter 2: Device- and Circuit-Level Modeling, Measurement, and Mitigation Chapter 3: Architectural Vulnerability Analysis Chapter 4: Advanced Architectural Vulnerability Analysis Chapter 5: Error Coding Techniques Chapter Please try the request again.

In: Proc of the 36th annual international symposium on computer architecture (ISCA ’09), Austin, TX, USA, pp 233–244 CrossRefGoogle Scholar3. SIGARCH Comput Archit News 33(4). Robert, Manish Parashar, Ramamurthy Badrinath, Viktor K. J Comput Sci Technol 6:1–7 Google Scholar5.

In: Proc of the IEEE 14th int’ symp on high performance computer architecture (HPCA’08), Salt Lake City Google Scholar10. PrasannaSpringer, 18.12.2006 - 642 Seiten 0 Rezensionen book constitutes the refereed proceedings of the 13th International Conference on High-Performance Computing, HiPC 2006, held in Bangalore, India, December 2006. URL 18. Olukotun K, Nayfeh BA, Hammond L, Wilson K, Chang K (1996) The case for a single-chip multiprocessor.

Copyright © 2016 ACM, Inc. Martínez JF, Renau J, Huang MC, Prvulovic M, Torrellas J (2002) Cherry: checkpointed early resource recycling in out-of-order microprocessors.