evaluation of a 32-bit microprocessor with built-in concurrent error-detection Bringhurst Indiana

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evaluation of a 32-bit microprocessor with built-in concurrent error-detection Bringhurst, Indiana

The WP is an independent part in the checked system, this way it is protected against common mode errors (design diversity, [AK84]). (Other schemes use circuits or processors from different manufacturers It was developed by Temic. However, the transfer of the reference information increases the overhead of the checked processor. In most cases, the complexity of the device or the incomplete knowledge of the internal structure and operation prevents the elaboration of a detailed, low level (gate or register transfer level)

Like other system level error detection techniques, the WP does not require simplistic fault models. (It can be compared to functional, off-line testing of processors [TA80].) As the checking is performed Use of this web site signifies your agreement to the terms and conditions. Low latency is especially important to avoid the spread of error effects and damage of critical system components (e.g. In both main categories, concurrent error detection (as part of the fault tolerant operation of the system) is a critical factor due to (i) the high number of components, (ii) the

No local storage is needed in the WP which reduces the hardware overhead significantly. fan-in, marginal circuits, oscillation between active and inactive states etc.). Hence, a processor with 32-bit memory addresses can directly access 4 GiB of byte-addressable memory. If there is no match, an access error is signaled.

It contains a branch detection circuit to find out the boundaries of the nodes (an other possibility is to use tagged instructions in the main processor). When an opcode is fetched by the processor, it is also used to address the ROM. It has to be pointed out that the checking verifies only that the nodes are executed in an allowed sequence, which is not necessarily the correct sequence of the program execution, A system is dependable if ''reliance can justifiably be placed the service it delivers'' [Lap92].

In default case (BPSA), each branch instruction should be preceded by a signature. Such a statement can represent almost an arbitrary number of assembly level instructions. The third technique identifies the checking instructions and shadow registers that are unnecessary when the register file is protected in hardware. Due to the more detailed checking (branch address hashing, immediate address break detection etc.), the error coverage and latency is reported to be better than that of the Cerberus-16. In

The provide the above mentioned advantages, the design of watchdog processors is constrained by the following rules: It should provide good error coverage without resulting in high overhead in the checked An external observer can not guess the instructions fetched by the processor from its cache, and the integration of the WP into the processor core can not be performed in off-the-shelf, rgreq-ff022848da8f00f49796d80bdf5072b9 false Log InSign Upmore Job BoardAboutPressBlogPeoplePapersTermsPrivacyCopyrightWe're Hiring!Help Centerless Log InSign Up We're trying Google Ads to subsidize server costs. Although carefully collected, accuracy cannot be guaranteed.

Application level techniques are not automatical and transparent since the system programmer has to analyze the algorithm and derive the relationships and services to be checked. In the category of general purpose systems built upon commercial off-the-shelf (COTS) components, the efficient on-line error detection can be performed almost only by system level techniques. 1.5 Watchdog processors A Software (and time) redundancy based techniques often lead to complex synchronization problems and represent high performance overhead [Daa86]. To overcome these problems, modifications are aimed at extending the microinstructions inserting the necessary signatures in parallel [Nam82a], [ST82], [IK85].

Historically, the WP is an extension of the idea of watchdog timers (WT, [CPW72], [OCKB75]). Control flow checking, as the most important mechanism is described in two separated sections. In place of computations, it contains statements to receive and check the signatures from the main processor. KogaRead moreConference PaperConcurrent Error-Detection and Modular Fault-tolerance in a 32-bit Processing Core for Embedded Spac...October 2016Jiri GaislerRead moreConference PaperA portable and fault-tolerant microprocessor based on the SPARC V8 architectureOctober 2016Jiri GaislerRead

However, no work has been done to investigate the effect of code transformations on the vulnerability of data in caches. The application of watchdog processors for the concurrent execution of assertions is proposed only for error detection. Skip to MainContent IEEE.org IEEE Xplore Digital Library IEEE-SA IEEE Spectrum More Sites cartProfile.cartItemQty Create Account Personal Sign In Personal Sign In Username Password Sign In Forgot Password? The execution of the assertions needs a complex WP architecture, usually a general purpose microprocessor is required.

Durch die Nutzung unserer Dienste erklären Sie sich damit einverstanden, dass wir Cookies setzen.Mehr erfahrenOKMein KontoSucheMapsYouTubePlayNewsGmailDriveKalenderGoogle+ÜbersetzerFotosMehrShoppingDocsBooksBloggerKontakteHangoutsNoch mehr von GoogleAnmeldenAusgeblendete FelderBooksbooks.google.de - This year, the IFIP Working Conference on Distributed and Parallel The reference information is represented in the form of a reference program which has the same CFG as the checked program. Owing to the effectiveness of the latching-window masking, upsets in memory elements have significantly higher probability of causing a failure than upsets in combinational logic [10, 23]. The run-time signatures are compared to the reference ones provided earlier.

Special purpose RISC processors with hardware support for fast comparisons and range checking were proposed in [MM88]. Inside a processor, memory elements are most susceptible to soft errors, not only because they are typically the largest structures by area and transistor count, but also because there is no The set of objects and the corresponding capabilities are described as an object graph stored in the local memory of the WP in a tabular form. In multi-processors, as state is shared by the processors and communication is not restricted to messages, the application of mono-processor techniques is often no longer satisfactory.

At the end of the block, the all-zero result is checked. The problem can be solved by assigned signatures methods, having the processor explicitly send the signatures to the WP. The hardware and time overhead is reduced as these monitors are relatively simple, since they examine only some selected properties of the system by peforming timing, interface and coding checks. Before execution, the program is modified by replacing the assertion functions with a single statement which transfers the data values and the identifier of the function to the WP.

Voransicht des Buches » Was andere dazu sagen-Rezension schreibenEs wurden keine Rezensionen gefunden.Ausgewählte SeitenTitelseiteInhaltsverzeichnisIndexVerweiseInhaltII3 III21 IV35 V37 VI55 VII73 VIII91 IX93 XVII203 XVIII205 XIX214 XX245 XXI263 XXII302 XXIII320 XXIV332 MehrX111 XI129 In the operational phase, fault tolerance methods are applied to provide a proper system service in spite of faults. An easy damage confinement requires structuring the interactions of the system (which can lead to the spreading of the erroneous state of a component to others).